1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device in which the emitter resistance is reduced.
2. Description of the Related Art
With reference to FIGS. 7A to 7C, a known semiconductor device will be described taking an npn-type transistor as an example.
FIG. 7A is a schematic diagram of the whole of a semiconductor element 100. FIG. 7B is a plan view of an electrode structure in a first layer, and dashed lines indicate electrodes in a second layer. FIG. 7C is a cross-sectional view taken along the E-E line of FIG. 7B.
A collector region 52 is provided on an n+ type silicon semiconductor substrate 51 by, for example, growing an n-type epitaxial layer or the like. In the surface of the collector region 52, a base region 53, which is a p-type impurity region, is provided. In the surface of the base region 53, an emitter region 54 is formed by diffusing n+-type impurities in the form of a grid. Thus, the base region 53 is separated into island-shaped patterns, and the island-shaped patterns and the emitter region 54 are arranged alternately. Incidentally, the separation into the island-shaped pattern is in apparent structure, and the base region 53 formed deeper than the emitter region 54 is a continuous region in a deeper region.
Hereinafter, the transistors formed of the base region 53 divided into the island-shaped patterns as described above and the emitter region 54 around the island-shaped patterns are referred to as cells, and the region in which a large number of cells are arranged is referred to as an operating region 58.
A base electrode and an emitter electrode which are connected to the base regions 53 and the emitter region 54 have two-layer structures, respectively.
First base electrodes 56 partially constituting the first layer are provided to form an island-shaped pattern and a strip pattern, and are in contact with the base regions 53 through first base contact holes BC1 provided in a first insulating film 25. A first emitter electrode 57 is provided in the form of a grid, and is in contact with the emitter region 54 through a first emitter contact hole EC1 provided in the first insulating film 25.
A second base electrode 66 and a second emitter electrode 67 constituting a second layer are provided above the first base electrodes 56 and the first emitter electrode 57 and connected thereto through second base contact holes (not shown) and second emitter contact holes EC2 (not shown) which are provided in a second insulating film 26.
The second base electrode 66 is provided over all the island-shaped first base electrodes 56 and parts of the strip-shaped first base electrodes 56, and is in contact therewith. The second emitter electrode 67 is provided over the strip-shaped first base electrodes 56 and is in contact with the first emitter electrode 57.
The second base electrode 66 and the second emitter electrode 67 are formed into the shapes of flat plates which cover the electrodes in the first layer as described above, and wire bonding is performed on these electrodes in the second layer, thus making it possible to expand a region in which wire bonding can be performed and to improve versatility in assembly. Further, since the second base electrode 66 and the second emitter electrode 67 are adjacent to each other only at respective one of the edges of the rectangles thereof, it is only necessary to take these parts into consideration in terms of difference in mask alignment and a clearance for obtaining a desired resist pattern. This technology is described for instance in Japanese Patent Application Publication No. 2000-40703.
FIG. 8 shows a case of mounting the aforementioned semiconductor chip 100.
There are cases where both of a base terminal B and emitter terminals E are arranged along one edge of the chip (lower edge of the chip in the drawing), for example, as shown in FIG. 8, in an assembly process. In those cases, since external terminals (e.g. leads) 200 arranged along one edge of the chip are connected to the second emitter electrode 67 and the second base electrode 66, these can be connected using bonding wires 150 as shown in the drawing in the case of an electrode structure in which the electrodes in the second layer have the shapes of flat plates.
Here, a reduction in emitter resistance is desirable for the improvement in characteristics of a bipolar transistor. Accordingly, efforts including, for example, securing a large area of the second emitter electrode 67 and making bonding wires as short as possible, are made.
Moreover, in particular, with the trend toward thinner packages, there are demands for a lower loop of a bonding wire. Accordingly, in some cases, the wire bond positions are set to the vicinity of an edge portion of the chip as shown in the drawing so that the low loops do not come into contact with the chip edge portion.
However, depending on the positions of the contact holes for connecting the electrodes in the first layer and in the second layer, parts to be current paths include a two-layer part formed of the first emitter electrode 57 and the second emitter electrode 67 and a one-layer part formed only of the second emitter electrode 67. In the case where the wire bond positions are in a chip edge portion, the emitter resistance from, for example, the part of the first emitter electrode 57 on the upper edge side in the drawing, to the wire bond position, becomes high. Accordingly, there has been the problem of a reduction in emitter resistance or the thinning of a chip being not developed.